1. Field of the Invention
This invention relates to the field of integrated circuit layout. More particularly, this invention relates to integrated circuit layout suitable for cross-coupled circuits.
2. Description of the Prior Art
A frequent circuit primitive within integrated circuits involves the cross-coupling of signals used to control the gates in adjacent diffusion regions. A sequence of gates formed along a first diffusion region will have a given sequence of signals controlling those gates and in a second adjacent diffusion region it is efficient to provide gates with control signals following the same sequence so that the gate layers can extend between the diffusion regions. However, in the case of cross-coupled circuits, which in practice are quite common, the order of two signals is reversed in one diffusion region compared with another diffusion region.
FIG. 1 illustrates a known layout solution to the above cross-coupling problem. In this solution a first diffusion region 2 is formed in a substrate substantially parallel to a second diffusion region 4. A sequence of gate layers 6, 8, 10, 12 (typically formed of polysilicon) are then formed overlapping the diffusion regions 2, 4 as shown. Where a gate layer 6, 8, 10, 12 overlaps a diffusion region 2, 4 there is formed a gate electrode 14, 16, 18, 20, 22, 24, 26 and 28. As illustrated, the sequence of control signals for the gate electrodes 14, 16, 18, 20 of the first diffusion region 2 (considered from left-to-right as shown in FIG. 1) includes the control signal sequence “A” followed by “B” in respect of the gate electrodes 16, 18. This ordering of control signals is reversed in respect of the gate electrodes 24, 26 formed on the second diffusion region 4.
In order to accommodate this cross-coupling it will be seen that the gate layer 8 has a rectilinear form including a portion running parallel to the first diffusion region 2 and the second diffusion region 4. The gate layer 10 is connected via a bridging conductor 30 formed in the first metal layer deposited over the gate layers 6, 8, 10, 12 so as to connect to the remaining portion of this gate layer 10′ formed overlapping the second diffusion region 4. The bridging conductor 30 is accordingly also rectilinear.
The spacing requirements of the rectilinear gate layer 8, the bridging conductor 30, the connections from the bridging conductor 30 down to the gate layer 10, 10′ and the connections to the diffusion region are such that one pitch of gate layers (a polysilicon pitch) must be missed between the gate layers 8 and 10, 10′. This has the result that the structure of FIG. 1 consumes four polysilicon pitches.
An increasingly severe problem with the arrangement of FIG. 1 is that the rectilinear form of the gate layer 8 is becoming difficult to accurately form as the device geometries shrink in size. With a 45 nm process, the rectilinear form is problematic to form with the existing processing techniques, such as the existing lithography. However, as process geometry sizes progress downward toward 32 nm and 22 nm the rectilinear form of gate layer 8 illustrated in FIG. 1 represents a significant problem to accurately form. Similar difficulties arise with the bridging conductor 30, although these are not quite so severe as with the gate layer 8.